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| FEDS81V05200-01 1 Semiconductor MS81V05200 (583,680-word x 10-bit) FIFO memory This version: Jun. 2001 GENERAL DESCRIPTION The MS81V05200 is a 5.6Mb FIFO (First-In First-Out) memory designed for 583,680-words x 10-bit high-speed asynchronous read/write operation. The MS81V05200 is best suited for a field memory for digital TVs or LCD panels which require high-speed, large memory, and is not designed for high end use in professional graphics systems, which require long term picture storage and data storage. The MS81V05200 is provided with independent control clocks to support asynchronous read and write operations. Different clock rates are also supported, which allow alternate data rates between write and read data streams. The first data read operation can be performed after 1600 ns + 4 cycles from read reset and the first data write operation is enabled after 1600 ns + 4 cycles from write reset. Thereafter, the high-speed read/write operation is possible every cycle time. Additionally, a write mask function by IE pin and a read-data skipping function by OE pin implement image data processing easily. The MS81V05200 provides high speed FIFO (First-in First-out) operation without external refreshing: MS81V05200 refreshes its DRAM storage cells automatically, so that it appears fully static to the users. Moreover, fully static type memory cells and decoders for serial access enable the refresh free serial access operation, so that serial read and/or write control clock can be halted high or low for any duration as long as the power is on. Internal conflicts of memory access and refreshing operations are prevented by special arbitration logic. The MS81V05200's function is simple, and similar to a digital delay device whose delay-bit- length is easily set by reset timing. The delay length and the number of read delay clocks between write and read, is determined by externally controlled write and read reset timings. The MS81V05200 uses a thin and small 70-pin plastic TSOP. FEATURES * * * * * * * 583,680 words x 10 bits Fast FIFO (First-In First-Out) operation: 13 ns cycle time Self refresh (No refresh control is required) High speed asynchronous read/write operation Variable length delay bit (600 to 583,680) Single power supply: 3.3 V 0.3 V Package: 70-pin plastic TSOP TYPE II (TSOP(2) 70-P-400-0.5-K) PARAMETERS Parameter Access Time Read/Write Cycle Time Operation Current Standby Current Symbol tAC tSWC tSRC ICC1 ICC2 MS81V05200-TA 8 ns 13 ns 200 mA 6 mA 1/25 FEDS81V05200-01 1 Semiconductor MS81V05200 PIN CONFIGURATION (TOP VIEW) VCC CS CSMODE NC VSS DI0 DI1 NC DI2 VSS DO0 DO1 VCC NC DO2 VSS VSS VCC VCC DO3 NC VCC NC DO4 VSS DI3 NC NC DI4 VSS OE RE RSTR SRCK VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 VSS NC NC NC VCC DI9 DI8 NC DI7 VSS DO9 DO8 VCC NC DO7 VSS VSS VCC VCC DO6 NC VCC NC DO5 VSS DI6 NC NC DI5 VCC IE WE RSTW SWCK VSS 70-pin Plastic TSOP SWCK SRCK WE RE IE OE RSTW RSTR DI0-9 DO0-9 CS CSMODE VSS VCC NC Serial Write Clock Serial Read Clock Write Enable Read Enable Input Enable Output Enable Reset Write Reset Read Data Input Data Output Chip Select Chip Select Mode Ground (0 V) Power Supply (3.3 V) No Connection Note: The same power supply voltage must be provided to every VCC pin, and the same GND voltage level must be provided to every VSS pin. 2/25 FEDS81V05200-01 1 Semiconductor MS81V05200 BLOCK DIAGRAM DO (X10) OE RE RSTR SRCK Data-output Buffer Serial Read Controller Read Data Register (X10) 583,680 x 10 Memory Array X Decoder Read/Write Refresh Timing Generator (X16) Write Data Register Refresh Counter Data-input Buffer Serial Write Controller DI (X10) IE WE RSTW SWCK 3/25 FEDS81V05200-01 1 Semiconductor MS81V05200 PIN DESCRIPTION Data Inputs: (DI0-9) These pins are used for serial data inputs. Write Reset: RSTW The first positive transition of SWCK after RSTW becomes high resets the write address pointers to zero. RSTW setup and hold times are referenced to the rising edge of SWCK. Write Enable: WE WE is used for data write enable/disable control. WE high level enables the input, and WE low level disables the input and holds the internal write address pointer. There are no WE disable time (low) and WE enable time (high) restrictions, because the MS81V05200 is in fully static operation as long as the power is on. Note that WE setup and hold times are referenced to the rising edge of SWCK. The latency for the write operation control by WE is 4. After write reset, WE must remain low for more than 1600 ns (tFWD). After write reset, the write operation at address 0 is started after a time tWL form the cycle in which WE is brought high. Input Enable: IE IE is used to enable/disable writing into memory. IE high level enables writing. The internal write address pointer is always incremented by cycling SWCK regardless of the IE level. Note that IE setup and hold times are referenced to the rising edge of SWCK. The latency for the write operation control by IE is 4. Data Out: (DO0-9) These pins are used for serial data outputs. Read Reset: RSTR The first positive transition of SRCK after RSTR becomes high resets the read address pointers to zero. RSTR setup and hold times are referenced to the rising edge of SRCK. Read Enable: RE The function of RE is to gate of the SRCK clock for incrementing the read pointer. When RE is high before the rising edge of SRCK, the read pointer is incremented. When RE is low, the read pointer is not incremented. RE setup times (tRENS and tRDSS) and RE hold times (tRENH and tRDSH) are referenced to the rising edge of the SRCK clock. The latency for the read operation control by RE is 4. After read reset, RE must remain low for more than 1600 ns (tFRD). After read reset, the read data at address 0 is output after a time tRL from the cycle in which WE is brought high. Output Enable: OE OE is used to enable/disable the outputs. OE high level enables the outputs. The internal read address pointer is always incremented by cycling SRCK regardless of the OE level. Note that OE setup and hold times are referenced to the rising edge of SRCK. The latency for the read operation control by OE is 4. Serial Write Clock: SWCK The SWCK latches the input data on chip when WE is high, and also increments the internal write address pointer. Data-in setup time tDS, and hold time tDH are referenced to the rising edge of SWCK. Serial Read Clock: SRCK Data is shifted out of the data registers. It is triggered by the rising edge of SRCK when RE is high during a read operation. The SRCK input increments the internal read address pointer when RE is high. The three-state output buffer provides direct TTL compatibility (no pullup resistor required). Data out is the same polarity as data in. The output becomes valid after the access time interval tAC that begins with the rising edge of SRCK. *There are no output valid time restriction on MS81V05200. 4/25 FEDS81V05200-01 1 Semiconductor MS81V05200 ABSOLUTE MAXIMUM RATINGS Parameter Power Supply Voltage Input Output Voltage Output Current Power Dissipation Operating Temperature Storage Temperature Symbol VCC VT IOS PD TOPR TSTG Condition Ta = 25C Ta = 25C, VSS Ta = 25C Ta = 25C -- -- Rating -0.5 to +4.6 -0.5 to +4.6 50 1 0 to 70 -55 to +150 Unit V V mA W C C RECOMMENDED OPERATING CONDITIONS Parameter Power Supply Voltage Input High Voltage Input Low Voltage Symbol VCC VIH VIL Min. 3.0 2.0 -0.3 Typ. 3.3 VCC 0 Max. 3.6 VCC + 0.2 0.8 Unit V V V ELECTRICAL CHARACTERISTICS DC Characteristics Parameter Input Leakage Current Output Leakage Current Output "H" Level Voltage Output "L" Level Voltage Operating Current Standby Current Symbol ILI ILO VOH VOL ICC1 ICC2 Condition 0 < VI < VCC, Other Pins Tested at V = 0 V 0 < VO < VCC IOH = -2 mA IOL = 2 mA Minimum Cycle Time Output Open Input Pin = VIH/VIL Min. -10 -10 2.4 -- -- -- Max. +10 +10 -- 0.4 200 6 Unit A A V V mA mA Capacitance (VCC = 3.3 V 0.3 V, Ta = 25C, f = 1 MHz) Parameter Input Capacitance Output Capacitance Symbol CI CO Max. 5 7 Unit pF pF 5/25 FEDS81V05200-01 1 Semiconductor MS81V05200 AC Characteristics (VCC = 3.3 V 0.3 V, Ta = 0 to 70C) Parameter DOUT Access Time from SRCK DOUT Hold Time from SRCK DOUT Enable Time from SRCK SWCK "H" Pulse Width SWCK "L" Pulse Width Input Data Setup Time Input Data Hold Time WE Enable Setup Time WE Enable Hold Time WE Disable Setup Time WE Disable Hold Time IE Enable Setup Time IE Enable Hold Time IE Disable Setup Time IE Disable Hold Time WE "H" Pulse Width WE "L" Pulse Width IE "H" Pulse Width IE "L" Pulse Width RSTW Setup Time RSTW Hold Time SRCK "H" Pulse Width SRCK "L" Pulse Width RE Enable Setup Time RE Enable Hold Time RE Disable Setup Time RE Disable Hold Time OE Enable Setup Time OE Enable Hold Time OE Disable Setup Time OE Disable Hold Time RE "H" Pulse Width RE "L" Pulse Width OE "H" Pulse Width OE "L" Pulse Width RSTR Setup Time RSTR Hold Time SWCK Cycle Time SRCK Cycle Time Transition Time (Rise and Fall) WE "L" Period before W Reset RE "L" Period before R Reset RE Delay after Reset WE Delay after Reset Symbol tAC tDDCK tDECK tWSWH tWSWL tDS tDH tWENS tWENH tWDSS tWDSH tIENS tIENH tIDSS tIDSH tWWEH tWWEL tWIEH tWIEL tRSTWS tRSTWH tWSRH tWSRL tRENS tRENH tRDSS tRDSH tOENS tOENH tODSS tODSH tWREH tWREL tWOEH tWOEL tRSTRS tRSTRH tSWC tSRC tT tLWE tLRE tFRD tFWD Min. -- 3 3 4 4 3 1 3 1 3 1 3 1 3 1 4 4 4 4 3 1 4 4 3 1 3 1 3 1 3 1 4 4 4 4 3 1 13 13 1 4 4 1,600 1,600 Max. 8 -- 8 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 5 -- -- -- -- Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns clk clk ns ns 6/25 FEDS81V05200-01 1 Semiconductor MS81V05200 Parameter Write Latency Read Latency WE Write Control Latency IE Write Control Latency RE Read Control Latency OE Read Control Latency Symbol tWL tRL tWEL tIEL tREL tOEL Latency 4 4 4 4 4 4 Unit clk clk clk clk clk clk AC Characteristic Measuring Conditions Output Compare Level Output Load Input Signal Level Input Signal Rise/Fall Time Input Signal Measuring Reference Level 1.4 V 1 TTL + 30 pF 3.0 V/0.0 V 1 ns 1.4 V Note: Input voltage levels for the AC characteristic measurement are VIH = 3.0 V and VIL = 0 V. When transition time tT becomes 1 ns or more, the input signal reference levels for the parameter measurement are VIH (min.) and VIL (max.). 7/25 FEDS81V05200-01 1 Semiconductor MS81V05200 OPERATION MODE Write Operation Cycle The write operation is controlled by four control signals, SWCK, RSTW, WE, and IE. The write operation is accomplished by cycling SWCK, and holding WE high after the write address pointer reset operation or RSTW. RSTW must be performed for internal circuit initialization before write operation. WE must be low before and after the reset cycle (tLWE + tFWD). Each write operation, which begins after RSTW must contain at least 231 active write cycles, i.e., SWCK cycles while WE and IE are high. Settings of WE and IE to the operation mode of write address pointer and data input WE H H L IE H L X Internal write address pointer Incremented Halted Data input (Latency 4) Input Not input X indicates "don't care" Read Operation Cycle The read operation is controlled by four control signals, SRCK, RSTR, RE, and OE. The read operation is accomplished by cycling SRCK, and holding both RE and OE high after the read address pointer reset operation or RSTR. Each read operation, which begins after RSTR, must contain at least 231 active read cycles, i.e., SRCK cycles while RE and OE are high. RE must be low before and after the reset cycle (tLRE + tFWD). Settings of RE and OE to the operation mode of read address pointer and data output RE H H L L OE H L H L Internal read address pointer Incremented Halted Data output (Latency 4) Output High impedance Output High impedance Old/New Data Access There must be a minimum delay of 600 SWCK cycles between writing into memory and reading out from memory. If reading from the first field starts with an RSTR operation, before the start of writing the second field (before the next RSTW operation), then the data just written will be read out. The start of reading out the first field of data may be delayed past the beginning of writing in the second field of data for as many as 70 SWCK cycles. If the RSTR operation for the first field read-out occurs less than 70 SWCK cycles after the RSTW operation for the second field write-in, then the internal buffering of the device assures that the first field will still be read out. The first field of data that is read out while the second field of data is written is called "old data". In order to read out "new data", i.e., the second field written in, read reset must be input after write address 200 the delay between an RSTW operation and an RSTR operation must be at least 600 SRCK cycles. If the delay between RSTW and RSTR operations is more than 71 but less than 600 cycles, then the data read out will be undetermined. It may be "old data" or "new data", or a combination of old and new data. Such a timing should be avoided. When the read address delay is between more than 71 and less than 599 or more than 583,680, read data will be undetermined. However, normal write is achieved in this address condition. 8/25 FEDS81V05200-01 1 Semiconductor MS81V05200 TIMING DIAGRAM Write Cycle Timing (Write Reset) tWSWH tSWC 0 cycle SWCK tWSWL tRSTWS tRSTWH RSTW tDS tDH DI0-9 Dn-3 Dn-2 Dn-1 Dn tFWD tWL D0 D1 WE tLWE IE Write Cycle Timing (Write Enable) 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle SWCK tWWEL tWWEH WE tWENH tWDSH D1 D2 D3 D4 tWEL tWDSS D5 tWENS DI0-9 D0 D6 D7 RSTW L IE H 9/25 FEDS81V05200-01 1 Semiconductor MS81V05200 Write Cycle Timing (Input Enable) 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 cycle SWCK tWIEL tWIEH IE tIENH tIDSH D1 D2 D3 D4 tIEL tIDSS D5 tIENS DI0-9 D0 D10 D11 RSTW L WE H 10/25 FEDS81V05200-01 1 Semiconductor MS81V05200 Read Cycle Timing (Read Reset) tWSRH tSRC 0 cycle 1 cycle SRCK tWSRL tRSTRS tRSTRH tRL tAC RSTR DO0-9 Qn-3 Qn-2 Qn-1 Qn tFRD Q0 Q1 RE H OE tLRE Read Cycle Timing (Read Enable) 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle SRCK tWREL tWREH RE tRENH tRDSH DO0-9 Q0 Q1 Q2 Q3 Q4 tREL tRDSS Q5 tRENS tAC Q6 Q7 RSTR L OE H 11/25 FEDS81V05200-01 1 Semiconductor MS81V05200 Read Cycle Timing (Output Enable) 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 cycle11 cycle SRCK tWOEL tWOEH OE tOENH tODSH Q1 Q2 Q3 Q4 tOEL tODSS tDDCK DO0-9 Q0 Q5 tOENS tAC Q10 tDECK Q11 RSTR L RE H 12/25 Write Cycle Timing 1 Semiconductor 01 2 98 99 01 23 4 56 7 8 9 10 11 12 SWCK RSTW tFWD tWL tWEL WE B7 B8 B9 A0 A1 A2 A98 A99 A100 B0 B1 B2 B3 B4 B5 B6 DI0-9 tIEL B11 Xi IE FEDS81V05200-01 MS81V05200 13/25 Read Cycle Timing 1 Semiconductor 01 96 97 01 23 456 7 8 2 9 10 11 12 SRCK RSTR tFRD tRL tREL RE tAC B7 B8 B9 A0 A1 A2 A95 A96 A97 B0 B1 B2 B3 B4 B5 B6 DO0-9 tOEL B11 Xi OE FEDS81V05200-01 MS81V05200 14/25 i 0 1 2 96 97 98 199 200 201202 292 293 294 295 296 SWCK 1 Semiconductor RSTW tWL tFWD WE Read/Write Cycle Timing (New Data Read) DI0-9 A0 Read reset should be input after write address 200. A1 A2 Xi-3 Xi-2 Xi-1 Xi IE i The address difference is 600 or more and 583,679 or less. 0 1 2 96 97 SRCK RSTR tFRD tRL RE tAC Xi A0 A1 DO0-9 FEDS81V05200-01 MS81V05200 OE 15/25 i 0 1 2 SWCK 1 Semiconductor RSTW tFWD tWL Read/Write Cycle Timing (Old Data Read) WE DI0-9 A0 The address difference is 70 or less. A1 A2 Xi IE i 0 1 2 3 4 SRCK RSTR tFRD tRL RE DO0-9 Xi A0 A1 A2 A3 A4 FEDS81V05200-01 MS81V05200 OE 16/25 FEDS81V05200-01 1 Semiconductor MS81V05200 PIN DESCRIPTION Chip Select Mode (CSMODE) This pin determines the polarity of the Chip Select (CS) pin. Always connect the CSMODE pin to VCC or VSS or leave it open. Chip Select (CS) This pin enables or disables devices (RSTW, WE, IE, RSTR, RE, and OE). The polarity of the CS pin is dependent upon the level of the CSMODE pin. In case where the CSMODE pin is connected to VSS or left open: When Chip Select (CS) is high, the device is enabled and ready for read/write operation. When Chip Select (CS) is low, the device is disabled and the internal Write/Read Address Pointer stops. Writing in the device is suppressed. The output of the pin goes to high impedance. In case where the CSMODE pin is connected to VCC: When Chip Select (CS) is low, the device is enabled and ready for read/write operation. When Chip Select (CS) is high, the device is disabled and the internal Write/Read Address Pointer stops. Writing in the device is suppressed. The output of the pin goes to high impedance. CSMODE VSS or OPEN VCC CS H L H L Device state Enabled Disabled Disabled Enabled The write/read operation is reset as follows: In case where the CSMODE pin is connected to VSS or left open: On the rising edge of SWCK, a write operation is reset when both RSTW and CS are high. On the rising edge of SRCK, a read operation is reset when both RSTR and CS are high. In case where the CSMODE pin is connected to VCC: On the rising edge of SWCK, a write operation is reset when RSTW is high and CS is low. On the rising edge of SRCK, a read operation is reset when RSTR is high and CS is low. In this case, the CS setup time (tRWCSS/tRRCSS) and the CS hold time (tRWCSH/tRRCSH) must be satisfied relative to the rising edge of SWCK/SRCK in the reset cycle. When CS and CSMODE set the "Disabled" device state, the RSTW/RSTR input is invalid. Satisfy the following conditions before causing CS to make a transition: * Pull WE, IE, RE, and OE low respectively for times tWECSS, tIECSS, tRECSS, and tOECSS before causing CS to make a transition. * Enter five or more SWCK and SRCK cycles during times tWECSS, tIECSS, tRECSS, and tOECSS, and then cause CS to make a transition. (A write operation requires five cycles or more of tWLCSA and tWLCSB. A read operation requires five cycles or more of tRLCSA and tRLCSB.) * Cause CS to make a transition only when RSTW and RSTR are low. * Pull WE, IE, RE, and OE low respectively for times tWECSH, tIECSH, tRECSH, and tOECSH after causing CS to make a transition. 17/25 FEDS81V05200-01 1 Semiconductor MS81V05200 OPERATION MODES (See TIMING DIAGRAM) CS Control Timing 1 When CS makes a high-to-low transition after data of up to A4/C4 is written in or read from FIFO1, FIFO1 is disabled and FIFO2 is enabled. When CS makes a low-to-high transition after data of up to B7/D7 is written in or read from FIFO2, FIFO2 is disabled and FIFO1 is enabled again. Data is written or read starting at A5/C5 in FIFO1. (In the "Disabled" device state, the address pointer in the FIFO1 remains unchanged.) CS Control Timing 2 (At Reset) When RSTW or RSTR is input, write-reset or read-reset is applied only to FIFO2 since CS is low. (FIFO1 is not reset.) Therefore, when FIFO1 is enabled again, data is written or read starting at Ai+5/Ci+5 in FIFO1. CS Control Timing 3 (At Reset) When RSTW or RSTR is input, write-reset or read-reset is applied only to FIFO1 (FIFO2 is not reset.) Therefore, data is written or read starting at Bi/Di in FIFO2. When FIFO1 is enabled again, data is written or read again starting at A0/C0 in FIFO1 since the internal address pointer is already reset. Power-up and Initialization On power-up, the device is designed to begin proper operation after at least 200 s after Vcc has stabilized to a value within the range of recommended operating conditions. After this 200 s stabilization interval, the following initialization sequence must be performed. Because the read and write address pointers are undefined after power-up, a minimum of 330 dummy write operations (SWCK cycles) and read operations (SRCK cycles) must be performed, followed by an RSTW operation and an RSTR operation, to properly initialize the write and the read address pointer. 18/25 FEDS81V05200-01 1 Semiconductor MS81V05200 AC Characteristics (CS Control) Parameter CS-WE Setup Time CS-WE Hold Time CS-IE Setup Time CS-IE Hold Time CS-RE Setup Time CS-RE Hold Time CS-OE Setup Time CS-OE Hold Time CS "H" Pulse Width CS "L" Pulse Width SWCK-CS Setup Time at RSTW Cycle SWCK-CS Hold Time at RSTW Cycle SRCK-CS Setup Time at RSTR Cycle SRCK-CS Hold Time at RSTR Cycle Dummy SWCK Cycle before CS State Transition Final Dummy SWCK Period of CS Dummy SRCK Cycle before CS State Transition Final Dummy SRCK Period of CS Symbol tWECSS tWECSH tIECSS tIECSH tRECSS tRECSH tOECSS tOECSH tCSH tCSL tRWCSS tRWCSH tRRCSS tRRCSH tWLCSA tWLCSB tRLCSA tRLCSB Min. 68 23 68 23 68 23 68 23 4200 4200 8 8 8 8 4 13 4 13 Max. -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns clk ns clk ns 19/25 FEDS81V05200-01 1 Semiconductor MS81V05200 CS Control Circuit example 1) FIFO1 SWCK RSTW WE IE DI0-9 CS VSS or OPEN SWCK RSTW WE IE DI0-9 CS MS81V05200 CSMODE SRCK RSTR RE OE DO0-9 SRCK RSTR RE OE DO0-9 FIFO2 SWCK RSTW WE IE DI0-9 CS VCC MS81V05200 CSMODE SRCK RSTR RE OE DO0-9 20/25 FIFO2 ENABLE1 tWLCSA FIFO1 ENABLE1 tWLCSA FIFO1 ENABLE2 (continued from ENABLE1) SWCK (FIFO1/2) tWLCSB tWECSS tWECSH tWLCSB tWECSH tIECSS tIECSH CS Control Timing 1 1 Semiconductor RSTW (FIFO1/2) tWECSS WE (FIFO1/2) tIECSH tIECSS IE (FIFO1/2) DI0-9 (FIFO1) A5 A6 A7 A8 B0 B1 B2 B3 B4 B5 B6 B7 A0 A1 A2 A3 A4 DI0-9 (FIFO2) tRLCSA tRLCSA SRCK (FIFO1/2) tRLCSB tRECSH tOECSH tOECSS tRECSS tRECSH tOECSH tRLCSB RSTR (FIFO1/2) tRECSS RE (FIFO1/2) tOECSS OE (FIFO1/2) DO0-9 (FIFO1) tAC D0 D1 D2 C0 C1 C2 C3 C4 C5 C6 C7 C8 D3 D4 D5 D6 D7 DO0-9 (FIFO2) tCSL CS (FIFO1/2) CSMODE (FIFO1) VSS or OPEN FEDS81V05200-01 MS81V05200 CSMODE (FIFO2) VCC 21/25 FIFO1 ENABLE1 tWLCSA tWLCSB FIFO2 ENABLE1 (RESET operation) FIFO1 ENABLE2 (continued from ENABLE1) tWLCSA SWCK (FIFO1/2) tRWCSS tWLCSB tWECSS tIECSH tWECSH tFWD tIECSH tIECSS 1 Semiconductor RSTW (FIFO1/2) tWECSS WE (FIFO1/2) tIECSS CS Control Timing 2 (Reset Timing) IE (FIFO1/2) DI0-9 (FIFO1) Ai+5 Ai+6 Ai+7 Ai+8 Ai Ai+1 Ai+2 Ai+3 Ai+4 DI0-9 (FIFO2) B0 B1 B2 B3 B4 B5 tRLCSA tRLCSA tRRCSS tRLCSB tRECSS tOECSS tRECSH tOECSH tFRD tOECSH tRLCSB SRCK (FIFO1/2) RSTR (FIFO1/2) tRECSS RE (FIFO1/2) tOECSS OE (FIFO1/2) tAC Ci+5 Ci+6 Ci+7 Ci+8 DO0-9 (FIFO1) Ci Ci+1 Ci+2 Ci+3 Ci+4 DO0-9 (FIFO2) tCSL Di D0 D1 D2 D3 D4 D5 D6 D7 CS (FIFO1/2) CSMODE (FIFO1) VSS or OPEN FEDS81V05200-01 MS81V05200 CSMODE (FIFO2) VCC 22/25 FIFO1 ENABLE1 (RESET operation) FIFO2 ENABLE1 tWLCSA FIFO1 ENABLE2 (continued from ENABLE1) tWLCSA tWLCSB SWCK (FIFO1/2) tRWCSH tWLCSB tWECSH tIECSH tIECSS tIECSH tWECSS tWECSH 1 Semiconductor RSTW (FIFO1/2) tWECSS WE (FIFO1/2) tIECSS CS Control Timing 3 (Reset Timing) IE (FIFO1/2) DI0-9 (FIFO1) A0 A1 A2 A3 Bi Bi+1 Bi+2Bi+3 Bi+4 Bi+5 Ai Ai+1 Ai+2 Ai+3 Ai+4 Ai+5 DI0-9 (FIFO2) tRLCSA tRLCSA tRLCSB SRCK (FIFO1/2) tRRCSH tRLCSB tRECSS tOECSS tRECSH tOECSH tRECSH tOECSH RSTR (FIFO1/2) tRECSS RE (FIFO1/2) tOECSS OE (FIFO1/2) DO0-9 (FIFO1) tAC Di Di+1 Di+2 Di+3 Di+4 Di+5 Di+6 Ci Ci+1 Ci+2 Ci+3 Ci+4 Ci+5 C0 C1 C2 C3 DO0-9 (FIFO2) tCSL CS (FIFO1/2) CSMODE (FIFO1) VSS or OPEN FEDS81V05200-01 MS81V05200 CSMODE (FIFO2) VCC 23/25 FEDS81V05200-01 1 Semiconductor MS81V05200 PACKAGE DIMENSIONS (Unit: mm) TSOP(2)70-P-400-0.50-K Mirror finish 5 Notes for Mounting the Surface Mount Type Package Package material Lead frame material Pin treatment Package weight (g) Rev. No./Last Revised Epoxy resin 42 alloy Solder plating (5m) 0.49 TYP. 2/Nov. 13, 1998 The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki's responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 24/25 FEDS81V05200-01 1 Semiconductor MS81V05200 NOTICE 1. The information contained herein can change without notice owing to product and/or technical improvements. Before using the product, please make sure that the information being referred to is up-to-date. 2. The outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. When planning to use the product, please ensure that the external conditions are reflected in the actual circuit, assembly, and program designs. When designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. Neither indemnity against nor license of a third party's industrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. No responsibility is assumed by us for any infringement of a third party's right which may result from the use thereof. The products listed in this document are intended for use in general electronics equipment for commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). These products are not authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. Such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, and life-support systems. Certain products in this document may need government approval before they can be exported to particular countries. The purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these. No part of the contents contained herein may be reprinted or reproduced without our prior permission. Copyright 2001 Oki Electric Industry Co., Ltd. 3. 4. 5. 6. 7. 8. 25/25 |
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